This invention relates to data processing systems of the type which include a digital computer and a plurality of memory modules which are intercoupled to each other by a system bus; and more particularly, it relates to the detection of certain memory addressing errors which can occur in such systems.
In a data processing system of the above type, each memory module includes an array of storage cells which are selectively addressed by the digital computer. Thus, each memory module includes some logic circuitry which determines whether or not a particular address from the computer is for that module. For example, the first memory module might respond to addresses of the range 0 thru 2.sup.16 -1; the second memory module might respond to addresses 2.sup.16 thru 2(2.sup.16)-1; the third memory module might respond to addresses 2(2.sup.16) thru 3(2.sup.16)-1; etc.
In order for each memory module to respond to a certain range of addresses, each module must include some means for selectively assigning a particular range of addresses to that module. For example, the address range for a memory module can be held in a register on the module, or it can be indicated by the setting of several electro-mechanical switches on the module.
Now, a problem which the above described system is susceptible to is the possibility that through an error, two memory modules will be assigned the same address range. When that happens, the data processing system will still operate but at a reduced capacity.
Suppose for example, that the first and second memory modules are assigned the same address range. In that case, the first and second memory modules will perform their Read operations and Write operations on their data storage cells in parallel with each other; and, no memory error will be detected.
Consequently, the two memory modules can continue to operate in parallel for an indefinite period of time. In fact, if the reduced memory capacity of the data processing system is sufficient to run all of the computer's programs, then the error would stay undetected.
Accordingly, the primary object of the invention is to provide a novel memory module by which the above problem is overcome.